1. Field of the Invention
The present invention relates to a programmable logic device which permits a user to electrically program an arbitrary logic circuit manually, and more specifically to an improved programmable logic device, which includes highly versatile, or functional programmable wiring occupying a reduced area for connecting a plurality of programmable logic elements, the programmable logic elements with each other.
2. Description of the Prior Art
There is conventionally known a programmable logic device (hereinafter simply referred to as a PLD), that is an integrated circuit with which a user can construct an arbitrary logic circuit manually.
The prior PLD primarily includes a programmable logic element (hereinafter simply referred to as a PLE) which is configurable to construct a user's own logic, a circuit function-defining memory cell for defining the logic function of the PLE and an interconnection relation among internal wirings, a programmable input/output block (hereinafter simply referred to as an IOB) for interfacing between external device packaging pins and an internal logic circuit (i.e., the PLE), and programmable wiring for establishing a wiring path to connect input/output signals into/from the IOB and the PLE to a desired network.
The programmable wiring is hitherto comprised, as illustrated for example in FIG. 9, of horizontal wirings 12 disposed between adjacent lines of the respective PLEs 10 (and IOBs), vertical wirings 14 disposed between adjacent columns of the respective PLEs 10 (and IOBs), switching matrixes 16 including interwiring switches 16A each disposed at intersections of the lines and the columns of the respective horizontal and vertical wirings 12 and 14 for interconnecting the wirings from the adjacent columns and lines, and input/output switches (hereinafter referred to as IOSs) 18 each disposed at a position corresponding to the adjacent PLEs 10 of the respective wirings 12 and 14 for connecting inputs and outputs into and from the adjacent PLEs 10 to the wirings 12 or 14.
The interwiring switches 16A and IOS 18 are controllable by each bit of circuit function-defining data, respectively, for establishing arbitrary wiring.
However, since in such a prior PLD, the IOSs 18 of the respective PLEs 10 and the interwiring switches 16A are independently provided, interconnection between two PLEs 10 always requires two IOSs 18 and at least one switching matrix 18, whether the two PLEs are disposed far away from or adjacent to each other. This arrangement further requires an increased number of the switches and complicated wiring, resulting in the PLD occupying a large area. Additionally, there are required many gates or switches, through which associated signals pass, thereby attenuating the signals and lowering the reliability of the device.